Field
Embodiments described in the present specification relate to a semiconductor memory device configured as an arrangement of memory cells each storing data by a change in resistance value of a variable resistance element, and an operation method thereof.
Description of the Related Art
In recent years, a resistance varying memory device employing a variable resistance element as a storage element has been receiving attention as a successor candidate of flash memory. Now, it is assumed that the resistance varying memory device, as well as including a resistance varying memory in a narrow sense, that is, a resistance varying memory that configures a transition metal oxide as a recording layer and stores a resistance value state of the transition metal oxide in a nonvolatile manner (ReRAM: Resistive RAM), includes also a phase change memory that employs chalcogenide or the like as a recording layer and uses resistance value information of a crystalline state (conductor) and an amorphous state (insulator) of the chalcogenide or the like (PCRAM: Phase Change RAM), and so on.
A memory cell array in a resistance varying memory device has memory cells disposed at intersections of bit lines and word lines, each memory cell being configured from a variable resistance element and a current rectifier element such as a diode or the like. In such a memory cell array, selection of a memory cell can be performed using the current rectifier element such as a diode or the like. Moreover, it is also possible for a high-density memory cell array to be realized by alternately stacking the bit lines and word lines to configure a three-dimensional stacked arrangement of memory cell arrays.
A resistance state of a recording layer in a resistance varying memory is changed by applying a voltage/current to the recording layer. Therefore, during a write operation, unless it is quickly detected that the resistance state of the recording layer has changed and the voltage/current application discontinued, an excessive electrical stress is applied to the recording layer, whereby a functional decline of the recording layer occurs. Accordingly, when a write operation is executed on a memory cell to change the resistance state, it must be quickly detected that the resistance state of the variable resistance element in the memory cell has changed, and thereby avoid, as far as possible, application of an unnecessary operational voltage. Detection of a change in resistance value of the variable resistance element is performed by, for example, detecting a voltage value of the bit line connected to the memory cell. Preparing a certain reference voltage and detecting when there is a reversal in magnitudes of the voltage value of the bit line connected to the memory cell and the voltage value of the reference voltage allows the change in resistance value of the memory cell to be detected.
In a memory cell array having memory cells arranged at intersections of bit lines and word lines, when a write operation is executed on a selected memory cell, the voltage state of the selected bit line and the selected word line change according to a resistance state of non-selected memory cells surrounding the selected memory cell. In view of the change in voltage state of the selected bit line and the selected word line, the reference voltage must be designed with a considerable margin. This makes it difficult to set the reference voltage employed for detecting whether the resistance state of the selected memory cell has undergone transition or not. There is also a possibility that, in the case where the voltage value of the reference voltage deviates from the voltage of the bit line connected to the selected memory cell around a time of the operation, the change in resistance state cannot be accurately detected. As a result, an excessive voltage is applied to the selected memory cell resulting in the memory cell being destroyed.